The present invention relates generally to the formation of multiple levels of porous silicon for buried insulators and conductors in silicon device technologies using porous silicon metallization by chemical vapor deposition. More particularly, the present invention relates to fabrication techniques used to form fully or partially insulated buried conductors under single crystal silicon.
A number of well-established techniques exist for forming buried insulators in silicon and are documented in numerous publications on silicon-on-insulator (SOI) technology. Some of these techniques for forming buried insulators have also been explored for forming buried conductors. Recently, interest has centered around metallized porous silicon for silicon-on-conductor (SOC) fabrication techniques, integrated circuit metallization, and interconnections applications.
Analogous to implantation of oxygen in SIMOX (Separation by Implanted Oxygen) for SOI technology, implantation of metal ions to form buried conductors has also been studied. Implantation of oxygen ions at different energies to form layers of insulators has also been demonstrated. The combined implantation of both oxygen and metal ions at different depths in order to form an oxide-coated metal (i.e., insulated metal) layer, however, has not been reported This method is expected to suffer from technical difficulties worse than the drawbacks plaguing current SIMOX techniques for SOI. It would require a high-energy, high-current implanter capable of metal ion implantation; these implanters are not widely available. Furthermore, this method may also cause damage to the overlying Si. High-temperature annealing of the implantation damage is required. These temperatures are very high, in the range of 1300.degree. C., to achieve a reasonable quality silicon layer after oxygen ion implantation.
Another method for forming buried conductive layers is electrodeposition of metal within porous silicon layers. This method is unsuitable for extended lateral metallization because of pore mouth blockage by the metal deposit.
Another method of forming buried insulated conductors is by recrystallization of amorphous or polycrystalline silicon over an oxide-coated, high-temperature metal layer (e.g., tungsten). This technique has been used to realize three-dimensional integrated SOI circuits. A drawback to this technique is that the silicon quality produced by the recrystallization methods is generally inferior to those produced by the porous silicon methods. Furthermore, the recrystallization methods involve melting of the silicon, and thus require very high temperatures.
Although the SIMOX method is considered to be the frontrunning SOI technique for complementary-metal-oxide-silicon (CMOS) very large scale integrated (VLSI) circuits applications, it is widely recognized that porous silicon-based fabrication techniques offer unique advantages. Porous silicon-based SOI fabrication techniques can be classified into two types: (1) epitaxial deposition techniques, and (2) selective anodization techniques.
Epitaxial deposition techniques are attractive due to the uniformity of the porous silicon layer (PSL) and of the isolated island thicknesses. In these techniques, a uniform blanket layer of porous Si is first formed on the surface of the wafer. The surface PSL, which is single crystal, serves as the seeding layer for epitaxy of a fully dense device Si layer. Trenches are etched through the epitaxial layer down to the PSL, and the underlying PSL is later thermally oxidized through these trenches. Since the current flows in relatively straight parallel paths, the PSL is uniform and its characteristics can easily be adaptable to a variety of applications. A drawback to this method is that non-conventional low-temperature (&lt;750.degree. C.) epitaxy is required to avoid sintering of the pores and maintain their reactivity to oxidation. Low temperature expitaxy techniques such as plasma chemical vapor deposition of SiH.sub.4, molecular beam epitaxy (MBE), and liquid phase epitaxy have been used. So far, the crystalline quality of Si overlayers fabricated with this technique have been inferior to those fabricated by the selective buried anodization methods discussed below. Residual defects such as microtwins and dislocations originating from the PSL/epitaxial Si interface have been observed by cross-section transmission electron microscopy (XTEM).
Selective anodization techniques are characterized by selective formation of a porous silicon layer under the device Si layer. Typically, the heavily-doped n-type or p-type layer in n.sup.- /n.sup.+ /n.sup.- or n/p.sup.+ /p.sup.- doped structures is anodized and subsequently oxidized to form the buried insulator. Selective anodization methods to form silicon-on-insulator structures offer very low defect density device silicon layers, and the ability to form a wide range of overlying silicon and buried oxide layer thicknesses which may be optimized for smart-power applications (thick layers on the order of microns) or for high-speed CMOS applications (thin, less than one micron thick layers).